The present invention relates to a plasma processing apparatus and method, more particularly to a plasma processing apparatus and method suited to apply a bias voltage to a specimen.
In the conventional plasma etching technique of this type, as disclosed in JP-A-2-65131, it is known that the electrostatic damage has been prevented by providing an electrically conductive ring at a position surrounding the wafer.
As disclosed in JP-A-8-181107, there is known a technique that a surrounding ring formed of ceramic is provided around a lower electrode, a wafer is mounted on the surrounding ring so as to have a space between the wafer and the lower electrode and thereby have an electrostatic capacitance, so that a DC voltage generated in a plasma is distributed into the space, a blocking capacitor and the wafer to prevent occurrence of charging damage to the wafer.
However, the above conventional technique is insufficient to prevent the gate oxide film from the electrostatic damage when the gate oxide film becomes much thinner. Further, it is difficult for all the different processing objects such as different kinds of films, different working shapes such as grooves or holes to achieve both of reduced-damage property and desired etching characteristics within the wafer surface. The etching characteristics include uniformity of etching, etching shape, selectivities to mask and underlayer materials and etching rate.
That is, the semiconductor integrated circuit becomes more minute and more complex for obtaining much higher function and much higher-speed operation. In higher-speed semiconductor devices, the gate oxide film is much thinner, resulting in lower dielectric breakdown voltage as shown in FIG. 1. Thus, in dry etching conducting the plasma processing using charged particles or the like, it is possible that electrostatic damage occurs due to potential difference produced between gate oxide films unless the process is carried out while taking delicate balancing between positive (i.e., ions) and negative charged species (i.e., electrons).
This is because the potential of the wafer base material (silicon) is subjected to the average of the amount of electric charges flowing into the wafer from the plasma, while the potential of the gate oxide film is subjected to the amount of electric charges flowing into the gate oxide film from the local plasma just above the oxide film so that the slight difference in flowing amount of the electric charges over the whole wafer surface produces the potential difference between the areas above and under the oxide film or across the base material of silicon. This phenomenon is also called as “charging damage”.
This often occurs by the difference in amount of the flowing-in charged particles, which occurs, especially when the wafer bias voltage is applied, due to slight difference of the applied bias voltage caused by the difference in impedance to the earth between the wafer surface positions.
A conventional countermeasure against the above is to take a method of preventing the charging damage by using a conductive ring at an outer periphery of the wafer. However, since this method relies on a method of locally changing the plasma density at the periphery, it is difficult, in case of processing a wafer of large diameter of 12 inches or larger, to satisfactorily suppress the damage in the gate oxide film as the gate oxide film of the large-diameter wafer becomes more and more thin, because the area where the plasma density is balanced is small.
Also, when the above device is manufactured by using a wafer of a large diameter, it is required to maintain the etchant density uniform within the wafer surface in order to achieve uniformity of etching with respect to the shape over the wafer surface. Especially, in order to suppress the excess etchant at a peripheral part of a wafer of a large diameter, it has been done to provide an etchant consuming ring at the wafer periphery and applying a bias thereto thereby maintaining the uniformity over the surface.
However, the bias current flowing through the ring provided to the wafer periphery also causes the impedance of the wafer periphery to change, thereby changing the amount of electric charges flowing into the wafer which adversely affects the charging damage characteristics.
U.S. Pat. No. 5,535,507 issued to Barnes et al discloses a technique of compensating for unequality in etching of a workpiece by using an electrostatic chuck which supports the workpiece by electrostatic attracting force between the workpiece and an electrode. However, this U.S. Patent fails to teach a method of compensating for charging damage which is intended by the present invention.
JP-A-8-316212 discloses another technique in which an electrode portion of a wafer mount is divided into a plurality of electrically isolated areas, impedance matching elements are connected to respective areas so as to control the impedances thereof, and alternatively, a recessed portion is provided on the electrode surface of the wafer mount such that the impedances between the wafer and the electrode differ between the center portion and the outer portion of the electrode to make ion energy emitted to the wafer uniform over the entire surface, thereby achieving a uniform plasma process. However, this technique also does not refer to the compensation for charging damage.